The dimensions of semiconductor field effect transistors (FETs) have been steadily shrinking over the last thirty 30 years or so, as scaling to smaller dimensions leads to continuing device performance improvements. Planar FET devices have a conducting gate electrode positioned above a semiconducting channel, and electrically isolated from the channel by a thin layer of gate dielectric. Applying voltage to the conducting gate controls current through the channel.
For a given device length, the amount of current drive for an FET is defined by the device width (w). Current drive scales proportionally to device width, with wider devices carrying more current than narrower device. This idea is illustrated schematically in FIGS. 1A-1C. Specifically, FIGS. 1A-1C are cross sectional views of planar FETs including a semiconductor substrate 10, a gate dielectric 12 and a gate conductor 14. As shown, the FET of FIG. 1A has a device width w, the FET of FIG. 1B has a device width of 2w and the FET of FIG. 1C has a device width of 3w. In these devices, the width can be changed to any arbitrary value, as it is defined lithographically. Different parts of integrated circuits (ICs) require FETs to drive different amounts of current, i.e., with different device widths, which is particularly easy to accommodate in planar FET devices by merely changing the device gate width (using lithography).
With conventional planar FET scaling reaching fundamental limits, the semiconductor industry is looking at more unconventional device geometries, which will facilitate continued performance improvements. One such class of device geometries involves transforming the transistor's semiconducting channel from a planar sheet into an array of parallel channel elements. Single devices of this type have current flowing through multiple channel elements in parallel.
Devices utilizing such channel arrays come in different flavors, and can be summarized as follows:                a. finFET: In a typical finFET structure, one of the channel array elements is a semiconducting “fin” of width w and height h, where typically w<h. The gate dielectric and gate conductor are positioned around the fin such that current flows down the channel on the two sides of the fin (generally, finFETs do not use the fin top surface as part of the conducting channel).        b. tri-gate FET: In such a device, one of the channel array elements has width w and height h, with w˜h, or w>h. The gate dielectric and gate conductor are positioned around the channel such that current flows down the channel on three sides.        c. nanowire FET: In this device, one of the channel array elements has width w and height h roughly equal. That is, w˜h. Typically, in a nanowire FET, the gate dielectric and gate conductor are positioned around the channel such that current flows down the channel on three sides. In other implementations, the gate conductor and gate dielectric wrap all around the nanowire elements such that current flows down the entire nanowire perimeter. Nanowires are also often cylindrical rather than the cubic shape shown in FIG. 2.        
The channel array elements of the foregoing described devices are shown, for example, in FIG. 2, where reference numeral 16 denotes an insulator such as an oxide, and reference numeral 18 denotes a semiconductor such as, for example, Si, Ge, SiGe, GaAs, InAs, InP and other III/V or II/VI compound semiconductors.
Adjusting the current drive of any of these channel array FETs is not as straightforward as for the planar FET described above. One approach is to adjust the channel element (e.g., fin, tri-gate element, nanowires) dimensions for different devices, i.e., increasing h for some devices would increase their current drive relative to others. From a fabrication standpoint however, this approach is difficult and impractical.
Rather, current drive in these devices can be more easily adjusted using the scheme shown in FIGS. 3A-3C, where reference numeral 16 is an insulator, reference numeral 18 is a semiconductor, reference numeral 12 is a gate dielectric including, for example, SiO2, SiON, SiN, metal oxides, or mixed metal oxides, and reference numeral 14 is a gate conductor including polySi, a conductive elemental metal, an alloy including at least one conductive elemental metal, or a nitride or silicide of a conductive elemental metal. In these devices, current drive is increased by incrementally adding channel elements in parallel.
Specifically, the device shown in FIG. 3A is composed of one channel element, while the device shown in FIG. 3B contains two channel elements and the device shown in FIG. 3B contains three channel elements. Correspondingly, the device shown in FIG. 3C drives three times as much current (i.e., three times the device width) as the device shown in FIG. 3A. In these FETs, the device width w is controlled by adding channel discrete elements in parallel. The three devices shown in FIGS. 3A-3C have widths of 2h, 4h, and 6h, respectively. Arbitrarily large current drives can be achieved by adding channel elements to the device.
A main difficulty in fabricating any of these devices consisting of multiple channel elements (i.e., more than one fin, more than one nanowire, etc.) is in patterning and placement of the channel array elements. It is desirable that channel element widths (w) are small, i.e., in the range of 1-50 nm, which is below the limits of conventional lithographic techniques. Several specialized techniques can be used to pattern at these dimensions (described below), however these invariably come at a cost of being able to position the elements close to one another. In other words, it is extremely difficult to pattern small channel elements, which are also closely spaced. This combination is ideally sought for practical implementation of these channel array FET devices.
Generally speaking, formation of the channel array elements comprising these advanced FET designs requires patterning at sub-lithographic dimensions. While certainly there have been device demonstrations using different methods of high-resolution “research” types of lithography (such as electron-beam lithography), the discussion herein is limited to methods which are considered manufacturable. That is, methods that have a high-throughput, and are cost effective.
One approach is illustrated schematically in FIGS. 4A-4E. FIG. 4A shows a cross sectional view of a photoresist line 20 which has been patterned on top of a thin semiconducting layer 18; the semiconductor layer 18 lays atop an insulator 16. The photoresist 20 is “trimmed” in FIG. 4B by exposure to, for example, an O2 plasma. This removes organic resist from all sides (and top) exposed to the plasma, resulting in a linewidth reduction below the initially defined structure (shown in FIG. 4C). The remaining photoresist pattern 20 is transferred into the underlying semiconductor layer 18 by, for example, reactive-ion etching (RIE) (FIG. 4D), and finally the photoresist line 20 is removed (FIG. 4E).
This approach shown schematically in FIGS. 4A-4E works well for FET devices composed of a single channel element, however difficulties arise when adopting the technique to pattern devices composed of more than one element.
FIGS. 5A-5C show another approach that can be used in forming such FET devices. FIG. 5A shows the initial photoresist pattern for forming an FET of two channel array elements. In these drawing, elements 20, 18, and 16 are as described above in FIGS. 4A-4E. After the O2 trim to reduce linewidths, which is shown in FIG. 5B, the remaining structures have a large space between them (FIG. 5C). This is, of course, due to the fact that the feature center-positions cannot change during the O2 trim. In an optimal device, these channel array elements would be packed as tightly as possible.
Another method for forming sub-lithographic FET channel elements involves the use of what is known as “sidewall” processes, and is illustrated in FIGS. 6A-6I) and 7A-7C. Initially, a line 26 in a conventional first hard mask material (e.g., silicon dioxide) is formed using standard lithography and RIE on a stack containing semiconductor 18 and insulator 16 (FIG. 6A). Conformal deposition of a second hard mask material 28 (e.g., silicon nitride) on top of this structure results in the situation shown in FIG. 6B. An anisotropic etch of this second material 28 removes it from the semiconductor 18 as well as the top of the patterned line 26, while leaving material on the sides (FIG. 6C). Finally, the first hard mask material 26 can be selectively removed by, e.g., wet chemical etching, leaving only the free-standing sidewall material 28 (FIG. 6D). The width of these sidewall features is determined by the deposition thickness of the second material. Sidewall processes are difficult in practice, however there have been several demonstrations of devices based on such processes.
Sidewall processes do not naturally lend themselves to form channel elements (the process shown in FIGS. 6A-6D forms two sidewalls), however this difficulty can be sidestepped by careful consideration of the initial line patterning step. The technique encounters greater difficulty when patterning devices formed of more than two channel elements, as shown in FIGS. 7A-7C. This structure shows two lithographically-defined lines 30 atop a stack including layers 18 and 16 which result in 4 free-standing sidewalls 32 (FIG. 7C). As shown in FIGS. 7A-7C, sidewall processes also result in less-than-optimal device packing, and irregularly-spaced elements within a single device.
In view of the above, there is still a need for providing methods, which form structures which have inherent advantages over all prior art methods. That is, there is a need for providing channel array FET devices where each channel element has a width that is equal to or less than 50 nm, preferably less than 20 nm, and each channel array is comprised of elements where regular spacing between elements is equal to or less than 100 nm, preferably less than 40 nm.